Available at:

https://sourceforge.net/projects/logicsim/files/
-- 
~Mike

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Mmm, somebody heard my typing. ;-)

Pretty icon, BTW.

I did think about mentioning some of the more amusing features of this 
build... but I figured you already know about them anyway.

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On 6/14/2010 7:21 AM, Invisible wrote:
> Mmm, somebody heard my typing. ;-)
>
> Pretty icon, BTW.
>
> I did think about mentioning some of the more amusing features of this
> build... but I figured you already know about them anyway.

Do mention... I want to know.

What? the fact that if you wire a feeback loop the program just dies a 
horrible death?

The fact that no menus work yet?

The irritation that when you go and change something on the property 
grid the main window loses keyboard focus and it seems impossible to 
regain it?


Really.. I want to know the bugs, though, if it isn't those issues. If 
it is those issues, I'm aware of them. Right now I'm just trying to get 
the basic pieces in.

-- 
~Mike

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Mike Raiford wrote:
> On 6/14/2010 7:21 AM, Invisible wrote:
>> Mmm, somebody heard my typing. ;-)
>>
>> Pretty icon, BTW.
>>
>> I did think about mentioning some of the more amusing features of this
>> build... but I figured you already know about them anyway.
> 
> Do mention... I want to know.
> 
> What? the fact that if you wire a feeback loop the program just dies a 
> horrible death?
> 
> The fact that no menus work yet?
> 
> The irritation that when you go and change something on the property 
> grid the main window loses keyboard focus and it seems impossible to 
> regain it?

No, more things like...

- If you select "OR gate", it inserts a NOR gate.

- NAND has the same truth table as NOR.

- If you change an input's value from the property pane, the simulation 
doesn't update. (I didn't immediately notice the ability to "poke" the 
inputs to change them. It's also mildly irritating that you have to 
cycle through 0, 1 and Z.)

- You can't delete stuff, only add it. ;-)

- The selection marks look fine for 1-input gates, but for 2-input gates 
it looks kinda weird having a box between the two inputs.

I was espectially ticked by the first two - but I didn't wanna sound 
mean. ;-)

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On 6/14/2010 8:43 AM, Invisible wrote:
>
> No, more things like...
>
> - If you select "OR gate", it inserts a NOR gate.
>
> - NAND has the same truth table as NOR.

Crap! I must have screwed something up when building some of the other 
items... That's a regression error. I'll have to take care of that.

> - If you change an input's value from the property pane, the simulation
> doesn't update. (I didn't immediately notice the ability to "poke" the
> inputs to change them. It's also mildly irritating that you have to
> cycle through 0, 1 and Z.)

Yeah, the sim isn't updating right now when the properties are altered. 
There's reasons I'm not addressing this as of yet, mainly to do with the 
fact that I'm going to rewrite the simulation core, and at that point it 
won't matter how the property is altered.

Only if the input is 3-state do you have to cycle through the states.

> - You can't delete stuff, only add it. ;-)

Yeah, an annoyance for sure ... But, hey, pre-alpha. ;)

In truth I just haven't gotten around to coding some of the more trivial 
things, yet.

> - The selection marks look fine for 1-input gates, but for 2-input gates
> it looks kinda weird having a box between the two inputs.

The handles will eventually allow you to elongate the connecting pins, 
and change orientation by drag on gates. Its not there yet. It might 
make sense later, when it actually functions...

> I was espectially ticked by the first two - but I didn't wanna sound
> mean. ;-)

No! This is good stuff! I need feedback like this Obviously I miss 
things like this when coding the application.

-- 
~Mike

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>> - If you select "OR gate", it inserts a NOR gate.
>>
>> - NAND has the same truth table as NOR.
> 
> Crap!

Uh, yes. ;-) That's a kind of elementary mistake, right there. (Which is 
why I assumed you had already noticed it, but I guess not...)

> That's a regression error. I'll have to take care of that.

Yah. ;-)

>> - You can't delete stuff, only add it. ;-)
> 
> Yeah, an annoyance for sure ... But, hey, pre-alpha. ;)

Well, yeah. The thing I'm writing is currently just a few miles of 
function calls. It doesn't even *do* anything visible yet!

> In truth I just haven't gotten around to coding some of the more trivial 
> things, yet.

Ain't that always the way? ;-)

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I've just been prodding the 15-Jun build. I presume you know these 
already, but...

Adding a tristate buffer works, but not a tristate inverter. Also, 
neither the clock source nor the splitter work, but I guess that's 
intensional.

For the first time, I tried actually wiring together a simple circuit. 
Wiring seems to be quite buggy. Sometimes you join wires together and 
they don't actually join. Sometimes they look like they aren't joined, 
but when you connect the other end of the wire to something, suddenly it 
works. And sometimes it's difficult to figure out just what on Earth is 
going on. (Especially since you can't, say, delete the wires you've 
already made. *g*)

Still, I've spent several days now just trying to build the internal API 
to manage something like this, and I'm getting nowhere, rapidly...

-- 
http://blog.orphi.me.uk/
http://www.zazzle.com/MathematicalOrchid*

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On 6/14/2010 9:45 AM, Invisible wrote:
>>> - If you select "OR gate", it inserts a NOR gate.
>>>
>>> - NAND has the same truth table as NOR.
>>
>> Crap!
>
> Uh, yes. ;-) That's a kind of elementary mistake, right there. (Which is
> why I assumed you had already noticed it, but I guess not...)
>
>> That's a regression error. I'll have to take care of that.
>
> Yah. ;-)
>

Well, the NAND = NOR thing was a total cluster****, I don't know what I 
was thinking when I coded NAND. I have a feeling that code was probably 
written at 1:00am on a Saturday morning. How it got by me testing it is 
a total mystery. It was so obviously wrong for NAND.

The OR gate placing a NOR gate was interesting. I have a function that 
checks the types and caches the last used values for later use. Since 
OR, XOR and NOR all have the same basic drawing OR is the base class for 
those, only changing a few minor details (such as the extra curve on the 
input side of the XOR, and the output bubble on NOR), so, it would see 
that it could be cast to an OR and consequently dump it into the 
PreviousOrGate variable. Oops. I corrected the case with NOR, but 
discovered XOR only after I uploaded the code.

>
> Well, yeah. The thing I'm writing is currently just a few miles of
> function calls. It doesn't even *do* anything visible yet!
>

Your own sim? How is it going? ( as far as the function calls go, I guess? )


>> In truth I just haven't gotten around to coding some of the more
>> trivial things, yet.
>
> Ain't that always the way? ;-)

Yep.

-- 
~Mike

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>>>> - If you select "OR gate", it inserts a NOR gate.
>>>>
>>>> - NAND has the same truth table as NOR.
>>>
>>> Crap!
>>
>> Yah. ;-)
>>
> 
> Well, the NAND = NOR thing was a total cluster****, I don't know what I 
> was thinking when I coded NAND. I have a feeling that code was probably 
> written at 1:00am on a Saturday morning.

Oh, one of *those*... ;-)

I generally just don't code anything at that hour. It never ****ing 
works right anyway.

> How it got by me testing it is 
> a total mystery. It was so obviously wrong for NAND.

Heh, well, I did wonder. Actually, as I say, I just assumed that since 
it was *so* wrong, you must already know about it but just haven't got 
round to fixing it yet.

> The OR gate placing a NOR gate was interesting. I have a function that 
> checks the types and caches the last used values for later use. Since 
> OR, XOR and NOR all have the same basic drawing OR is the base class for 
> those, only changing a few minor details (such as the extra curve on the 
> input side of the XOR, and the output bubble on NOR), so, it would see 
> that it could be cast to an OR and consequently dump it into the 
> PreviousOrGate variable. Oops. I corrected the case with NOR, but 
> discovered XOR only after I uploaded the code.

Pah. Mutable state is evil! ;-)

>> Well, yeah. The thing I'm writing is currently just a few miles of
>> function calls. It doesn't even *do* anything visible yet!
> 
> Your own sim? How is it going? ( as far as the function calls go, I 
> guess? )

Very, very slowly. Like, I'm having trouble making it so that I can add 
and remove wires and stuff efficiently and still be able to look up what 
connects to what efficiently and...

(See my post about "highly redundant data structures.)

You, by comparison, have got something that *runs*. I'm still faffing 
around with design choices.

-- 
http://blog.orphi.me.uk/
http://www.zazzle.com/MathematicalOrchid*

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On 6/15/2010 1:53 PM, Orchid XP v8 wrote:

> Adding a tristate buffer works, but not a tristate inverter. Also,
> neither the clock source nor the splitter work, but I guess that's
> intensional.

Yep. Those aren't there yet.

> For the first time, I tried actually wiring together a simple circuit.
> Wiring seems to be quite buggy. Sometimes you join wires together and
> they don't actually join. Sometimes they look like they aren't joined,
> but when you connect the other end of the wire to something, suddenly it
> works. And sometimes it's difficult to figure out just what on Earth is
> going on. (Especially since you can't, say, delete the wires you've
> already made. *g*)

The problem, I think (aside from not being able to delete things...) is 
kind of two-fold... Connecting the pins while on the surface seemed very 
simple, some cases quickly become a royal PITA.... There are some 
modifier keys in wiring that will cause some of the connection stuff to 
behave differently, generally if it has an orange indicator, it should 
be connected when you release the mouse button. The other half of it is 
that it appears to have not connected because it doesn't always take the 
characteristics of what you just connected it to until the other end is 
connected to something else. This has more to do with the sim core, though.

There's also a major annoyance with-- for example-- altering the layout 
of a circuit. You pull a wire from one location, leaving 2 wires 
connected straight together, you then draw a new wire across that 
junction (which happens to be invisible...) and it joins everything at 
that intersection. One of the things I need to do is when reconciling 
the wires, ensure any wires that are joined at the same angle get 
consolidated into a single wire. After drawing wires for a few minutes I 
was able to slice and dice a single wire into a dozen pieces. Nasty.

> Still, I've spent several days now just trying to build the internal API
> to manage something like this, and I'm getting nowhere, rapidly...

That happens with lots of things ;)

-- 
~Mike

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