Am 18.05.2016 um 10:18 schrieb scott:
>> There is a fallacy here: In contrast to a bipolar transistor, where the
>> voltage drop is more or less constant, in a FET it is the resistance
>> that is more or less constant (and low but non-zero), while the voltage
>> drop may actually vary wildly, depending on the current flowing;
> 
> I thought the resistance (between source and drain) changes
> significantly as you change the gate voltage though? Otherwise how does
> a FET amplifier work? Like this one:

Yes, of course -- the resistance does indeed vary with gate voltage.
However, given a constant gate voltage (which is kind of a prerequisite
for the "digital on" state), the resistance across the drain-source
channel remains pretty much constant.


> http://newton.ex.ac.uk/teaching/CDHW/Electronics2/PHY2028-C16.1.gif
> 
> That's the bit I'm missing/not understanding. If the effective
> resistance (Vds/Id) is always a constant, near zero (much less than 10K
> I assume), then wouldn't that mean the outputs in that circuit (Vd and
> Vs) were always 7.5V or thereabouts?

No, that's a misunderstanding; when I said the resistance was constant
near-zero, I was referring to the "digital on" state. In the "digital
off" state, the resistance is also constant, but near-infinite, and if
the gate is driven with an alternating voltage as is customary in analog
circuitry, the resistance will vary with time.

But varying the drain-source voltage or current will not change the
resistance, so in that sense the resistance can be considered "constant"
(across the drain-source parameter space, rather than time) even in
analog operating modes.

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On 5/18/2016 2:48 PM, clipka wrote:
> Yes, of course -- the resistance does indeed vary with gate voltage.
> However, given a constant gate voltage (which is kind of a prerequisite
> for the "digital on" state), the resistance across the drain-source
> channel remains pretty much constant.

I thought Scott was talking about the linear amplification state.

Which is where this part of the thread started. Transistors have three 
states. On, off and in between. The in between state is always there 
even is the transition between on and off is very small. You even get 
ringing in FET circuits.



-- 

Regards
     Stephen

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On 5/18/2016 2:48 PM, clipka wrote:
 > Yes, of course -- the resistance does indeed vary with gate voltage.
 > However, given a constant gate voltage (which is kind of a prerequisite
 > for the "digital on" state), the resistance across the drain-source
 > channel remains pretty much constant.

I thought Scott was talking about the linear amplification state.

Which is where this part of the thread started. Transistors have three 
states. On, off and in between. The in between state is always there 
even is the transition between on and off is very small. You even get 
ringing in FET circuits.

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>> Yes, of course -- the resistance does indeed vary with gate voltage.
>> However, given a constant gate voltage (which is kind of a prerequisite
>> for the "digital on" state), the resistance across the drain-source
>> channel remains pretty much constant.
>
> I thought Scott was talking about the linear amplification state.
>
> Which is where this part of the thread started. Transistors have three
> states. On, off and in between. The in between state is always there
> even is the transition between on and off is very small. You even get
> ringing in FET circuits.

I *think* I understand clipka's point now though. In digital circuits, 
because the output of a FET is usually connected to something with 
extremely high impedance (eg the gate of another FET, or through another 
FET that is off), even in the "in between" state still almost no current 
will flow and hence no power will be dissipated.

This is in contrast to if you had a load (eg 1K) connected to the 
output. In this case, there will be almost no power dissipation in the 
FET if it is fully "on" (no voltage drop across the FET) or "off" (no 
current flow), but there will be in the linear amplification state (eg 
when the FET effective resistance matches the output load).

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Am 18.05.2016 um 16:51 schrieb scott:
>>> Yes, of course -- the resistance does indeed vary with gate voltage.
>>> However, given a constant gate voltage (which is kind of a prerequisite
>>> for the "digital on" state), the resistance across the drain-source
>>> channel remains pretty much constant.
>>
>> I thought Scott was talking about the linear amplification state.
>>
>> Which is where this part of the thread started. Transistors have three
>> states. On, off and in between. The in between state is always there
>> even is the transition between on and off is very small. You even get
>> ringing in FET circuits.
> 
> I *think* I understand clipka's point now though. In digital circuits,
> because the output of a FET is usually connected to something with
> extremely high impedance (eg the gate of another FET, or through another
> FET that is off), even in the "in between" state still almost no current
> will flow and hence no power will be dissipated.

Um... no. I was contesting the following statement of yours:

"[...] a transistor used in digital circuits is either in a state where
the current flow is zero ("off") OR the voltage drop is zero ("on"), so
heat output is usually zero."

More specifically, I contested the claim that the normally-zero heat
output in the "on" state was due to the magnitude of the voltage drop. I
made no claims about the "in between" state of the FET.

I may also like to point out that I did not address the case when
/another/ FET, with the drain-source channel wired in series with the
drain-source channel of the FET in question, is switched on. In that
case, a transient current does indeed flow through the FET in question,
and yes, if the FET in question is in fully "on" state, as long as the
other FET is still in the in-between state, that one will have a
sufficiently high resistance to bear the majority of power dissipation.

In such a transitory state of /other/ parts of the circuitry, a totally
switched-on FET will indeed not consume any noteworthy power thanks to a
much lower voltage drop /compared to its neighbor/ -- but power
consumption will still happen, namely in that neighbor.

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> Um... no. I was contesting the following statement of yours:
>
> "[...] a transistor used in digital circuits is either in a state where
> the current flow is zero ("off") OR the voltage drop is zero ("on"), so
> heat output is usually zero."
>
> More specifically, I contested the claim that the normally-zero heat
> output in the "on" state was due to the magnitude of the voltage drop.

So if you came up with some transistor where the output resistance was 
not near-zero in the "digital on" state, power consumption shouldn't be 
affected?

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Am 19.05.2016 um 09:11 schrieb scott:
>> Um... no. I was contesting the following statement of yours:
>>
>> "[...] a transistor used in digital circuits is either in a state where
>> the current flow is zero ("off") OR the voltage drop is zero ("on"), so
>> heat output is usually zero."
>>
>> More specifically, I contested the claim that the normally-zero heat
>> output in the "on" state was due to the magnitude of the voltage drop.
> 
> So if you came up with some transistor where the output resistance was
> not near-zero in the "digital on" state, power consumption shouldn't be
> affected?

Not in the stable state of the system, no.

Except maybe for the few transistors at the boundary to the outside
world, which may see pull-up resistors and external AC loads.


The system's behaviour during state switching is another matter of course.

Thanks to P=V^2/R, increasing the FETs resistance in the "digital on"
state would actually _reduce_ power consumption -- provided you kept
your design unchanged otherwise. However, switching delay would also
increase linearly with resistance, since you would also reduce the
current, and hence the amount of charge you could transfer to/from the
gates per unit of time.

To counteract that increase in switching time, you would have to
increase the voltage linearly, which would increase the power
consumption quadratically. Thanks to the aforementioned reduction in
power consumption from the increased R, you'd end up with the power
consumption increasing linearly with FET resistance if the operating
frequency is to remain the same.

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It's not connected to any actual quantum hardware, but I just ran across 
this nifty little quantum circuit simulator that you can run from within 
your browser: http://algorithmicassertions.com/2016/05/22/quirk.html

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> It's not connected to any actual quantum hardware, but I just ran across
> this nifty little quantum circuit simulator that you can run from within
> your browser: http://algorithmicassertions.com/2016/05/22/quirk.html

Neat, that looks way better than the IBM one [reads a bit more] oh wait 
yes he notices that too ;-)

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On 23/05/16 23:42, Kevin Wampler wrote:
> It's not connected to any actual quantum hardware, but I just ran across
> this nifty little quantum circuit simulator that you can run from within
> your browser: http://algorithmicassertions.com/2016/05/22/quirk.html

Thanks for the link, Kevin.

This is in the best traditions of hackerdom (in its old sense):
"I need a tool to do a job. The tools to do this job are either
expensive, inefficient, awkward to use or unavailable; therefore I will
build my own. I will also give it to the rest of the world for free."

Bravo, Craig Gidney

John
-- 
Protect the Earth
It was not given to you by your parents
You hold it in trust for your children

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