Am 18.05.2016 um 10:18 schrieb scott:
>> There is a fallacy here: In contrast to a bipolar transistor, where the
>> voltage drop is more or less constant, in a FET it is the resistance
>> that is more or less constant (and low but non-zero), while the voltage
>> drop may actually vary wildly, depending on the current flowing;
> 
> I thought the resistance (between source and drain) changes
> significantly as you change the gate voltage though? Otherwise how does
> a FET amplifier work? Like this one:

Yes, of course -- the resistance does indeed vary with gate voltage.
However, given a constant gate voltage (which is kind of a prerequisite
for the "digital on" state), the resistance across the drain-source
channel remains pretty much constant.


> http://newton.ex.ac.uk/teaching/CDHW/Electronics2/PHY2028-C16.1.gif
> 
> That's the bit I'm missing/not understanding. If the effective
> resistance (Vds/Id) is always a constant, near zero (much less than 10K
> I assume), then wouldn't that mean the outputs in that circuit (Vd and
> Vs) were always 7.5V or thereabouts?

No, that's a misunderstanding; when I said the resistance was constant
near-zero, I was referring to the "digital on" state. In the "digital
off" state, the resistance is also constant, but near-infinite, and if
the gate is driven with an alternating voltage as is customary in analog
circuitry, the resistance will vary with time.

But varying the drain-source voltage or current will not change the
resistance, so in that sense the resistance can be considered "constant"
(across the drain-source parameter space, rather than time) even in
analog operating modes.

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