Am 19.05.2016 um 09:11 schrieb scott:
>> Um... no. I was contesting the following statement of yours:
>>
>> "[...] a transistor used in digital circuits is either in a state where
>> the current flow is zero ("off") OR the voltage drop is zero ("on"), so
>> heat output is usually zero."
>>
>> More specifically, I contested the claim that the normally-zero heat
>> output in the "on" state was due to the magnitude of the voltage drop.
> 
> So if you came up with some transistor where the output resistance was
> not near-zero in the "digital on" state, power consumption shouldn't be
> affected?

Not in the stable state of the system, no.

Except maybe for the few transistors at the boundary to the outside
world, which may see pull-up resistors and external AC loads.


The system's behaviour during state switching is another matter of course.

Thanks to P=V^2/R, increasing the FETs resistance in the "digital on"
state would actually _reduce_ power consumption -- provided you kept
your design unchanged otherwise. However, switching delay would also
increase linearly with resistance, since you would also reduce the
current, and hence the amount of charge you could transfer to/from the
gates per unit of time.

To counteract that increase in switching time, you would have to
increase the voltage linearly, which would increase the power
consumption quadratically. Thanks to the aforementioned reduction in
power consumption from the increased R, you'd end up with the power
consumption increasing linearly with FET resistance if the operating
frequency is to remain the same.

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