>> Yes, of course -- the resistance does indeed vary with gate voltage.
>> However, given a constant gate voltage (which is kind of a prerequisite
>> for the "digital on" state), the resistance across the drain-source
>> channel remains pretty much constant.
>
> I thought Scott was talking about the linear amplification state.
>
> Which is where this part of the thread started. Transistors have three
> states. On, off and in between. The in between state is always there
> even is the transition between on and off is very small. You even get
> ringing in FET circuits.

I *think* I understand clipka's point now though. In digital circuits, 
because the output of a FET is usually connected to something with 
extremely high impedance (eg the gate of another FET, or through another 
FET that is off), even in the "in between" state still almost no current 
will flow and hence no power will be dissipated.

This is in contrast to if you had a load (eg 1K) connected to the 
output. In this case, there will be almost no power dissipation in the 
FET if it is fully "on" (no voltage drop across the FET) or "off" (no 
current flow), but there will be in the linear amplification state (eg 
when the FET effective resistance matches the output load).

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