In article <3ca7cb87@news.povray.org> , Warp <war### [at] tagpovrayorg>  wrote:

>   If the code being executed is modified, it invalidates the pipelines and
> perhaps even the code in the cache

There is a far more severe problem here:  All processor architectures
developed in the past 20 years (mostly RISC or VLIW ones of course) have
independent data and instruction caches as well as independent data and
instruction MMUs.  Consequently the modified *data* is in the data cache and
the processors has no idea it is supposed to be *code*.  In fact it cannot
know what it is.  The only reliable means the programmer has to be sure it
will be executed is to *flush* the data and instruction cache.

Intel, on the other hand, maintained a kind of internal common bus at least up
to the Pentium Pro.  That is, instruction and data cache share a common
interface to the actual bus interface.  On other architectures the bus
interface provides two separate busses - one to the data and one to the
instruction cache.  What this effectively implies is that until Intel somehow
changed the design (I have no idea how current P4s detect self-modifying code,
if they can do so efficiently at all!), the speed and efficiency of the
instruction cache was reduced.

>   Of course self-modification is ok if you first modify the code to be
> executed, and then this code is executed for a long period of time.

And it will flush the caches accordingly.  The same needs to be done for
just-in-time compilers.

    Thorsten

____________________________________________________
Thorsten Froehlich, Duisburg, Germany
e-mail: tho### [at] trfde

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