Le 20/07/2012 23:07, Orchid Win7 v1 nous fit lire :
> On 20/07/2012 09:31 PM, Darren New wrote:
>> On 7/20/2012 2:58, Le_Forgeron wrote:
>>> HT is: a second set of registers. Nothing more. No additional FPU or
>>> fancy integer units.
>>
>> This. Generally, the second core runs during cache misses of the first
>> core. The design intent was to help alleviate the problem of having main
>> memory RAM much slower than CPUs.
> 
> Really? I thought the design intent was to utilise idle execution units
> if a particular thread is hammering (say) only integer units, leaving
> the float units idle.

The "hammering" is no more: a single instruction is split in multiple
different steps, each using different parts. Each step take some cycles,
and some steps could be very long when compared to another.
Hence the possible reordering inside the pipeline, which was a bit
before they think of HT.

Take the instruction decoder: it ends up doing nothing while the FPU is
doing your division. Well... when the division is actually performed at
the FPU, the decoder is actually decoding the fourth or fifth
instruction after the division. Yet, bubbles of empty cycles happen on
the pipeline: your division was followed by an unrelated addition of two
integers... that addition took far less cycles than the division, so
instructions #2,#3,#4 and #5 have already been performed when #1 is
still running. Yet, result of#1 is now needed... and we have all these
decoder, ALU and all which are idle... Let's have a second thread of
execution, absolutely unrelated because it run another piece of code.
All we need is a second set of registers (dedicated) and some circuitry
to use the idle cycles of every sub-parts. (sound easy, it's a bit complex).

Post a reply to this message