On 20/07/2012 09:31 PM, Darren New wrote:
> On 7/20/2012 2:58, Le_Forgeron wrote:
>> HT is: a second set of registers. Nothing more. No additional FPU or
>> fancy integer units.
>
> This. Generally, the second core runs during cache misses of the first
> core. The design intent was to help alleviate the problem of having main
> memory RAM much slower than CPUs.

Really? I thought the design intent was to utilise idle execution units 
if a particular thread is hammering (say) only integer units, leaving 
the float units idle.

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