On 7/20/2012 2:58, Le_Forgeron wrote:
> HT is: a second set of registers. Nothing more. No additional FPU or
> fancy integer units.

This. Generally, the second core runs during cache misses of the first core. 
The design intent was to help alleviate the problem of having main memory 
RAM much slower than CPUs.

-- 
Darren New, San Diego CA, USA (PST)
   "Oh no! We're out of code juice!"
   "Don't panic. There's beans and filters
    in the cabinet."

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