On 9/14/2011 13:54, Orchid XP v8 wrote:
>> If it's automatic, why do x86 CPUs have memory fence instructions?
> I'm guessing that's for performance, not correctness.

http://software.intel.com/en-us/forums/showthread.php?t=65071

It appears at first google that you are correct. On second google,

http://siyobik.info/main/reference/instruction/LFENCE

I think what's happening is that I might write instructions that store 
things out of order, so I store something in a memory address, then store a 
pointer to that address some place you will look. On the x86 at least, the 
memory fence is necessary to make sure that I have stored the data before I 
have stored the pointer to it. You will always fetch the most recent pointer 
I have stored, but executing "store data ; store pointer" might store the 
pointer before the data without a fence. So it's not caches of main memory 
but caches of instruction results that's the issue I was thinking of.

-- 
Darren New, San Diego CA, USA (PST)
   How come I never get only one kudo?

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