On 12/09/2011 11:49 PM, Darren New wrote:
> On 9/12/2011 1:13, Invisible wrote:
>> (Think about it; if you did, every multi-threaded application ever
>> written
>> would suddenly break when run on a multi-chip or multi-core setup.)
>
> Not really. You have no more likelihood of breaking because of lack of
> memory barriers than you have of breaking because you've cached
> something in a register during a task switch.
>
> The compiler just has to write memory barrier instructions out when you
> access a volatile variable. That's why the keyword is there.

If you cache something in a register that you shouldn't have, your 
application will break on a uniprocessor system. And you'll notice this, 
and fix it.

If the hardware didn't enforce cache coherence, applications would work 
perfectly on a uniprocessor and then break spectacularly on a 
multiprocessor. This doesn't happen, ergo the hardware is enforcing 
cache coherence.

Post a reply to this message