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OK... something I don't get. Presumably, it has some weird thing to do
with alignment.
A bit of background first: The Pentium has a 64-bit data bus. What this
means is that the lower two bits of the address bus have been dropped.
Meaning, the processor really only accesses memory on 8 byte boundaries.
But, it has a way of getting around that, it has 8 pins that act as a
mask. If it only needs the first four bytes, then it can pull low only
the first four of the BE# pins. This tells the system's logic what it
wants. This makes accessing smaller chunks of memory much more efficient
if, say, the RAM is composed of modules that have an 8 bit data bus. Oh,
by the way... this is why it was critically important to make sure your
memory is installed in pairs. ;) You see, back in the day DRAM was sold
in 32 bit modules. With only one module installed, the data bus was only
32 bits wide (*IF* the motherboard actually supported that
configuration) but, with both....
But here's the part that isn't making sense to me:
>
+---------------------------------------------------------------------------------------------------------------+
> |Length of Transfer |1 Byte |2 Bytes
|
>
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~+
> |Low Order Address |xxx |000 |001 |010 |011 |100
|101 |110 |111 |
>
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~+
> |1st transfer |b |w |w |w |hb |w
|w |w |hb |
> |Value driven on A3 | |0 |0 |0 |0 |0
|0 |0 |1 |
>
+------------------------------+--------+--------+--------+--------+--------+--------+--------+--------+--------+
> |2nd transfer (if needed) | | | | |lb |
| |lb | |
> |Byte enables driven | | | | |BE3# |
| |BE7# | |
> |Value driven on A3 | | | | |0 |
| |0 | |
>
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~+
> |Length of Transfer |4 Bytes
|
>
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~+
> |Low Order Address | 000 |001 |010 |011 |100
|101 |110 |111 |
>
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~+
> |1st transfer | d |hb |hw |h3 |d
|hb | hw |h3 |
> |Low order address | 0 |0 |0 |0 |0 |1
|1 |1 |
>
+------------------------------+---------+---------+---------+----------+---------+---------+----------+--------+
> |2nd transfer (if needed) | |l3 |lw |lb |
|l3 |lw |lb |
> |Value driven on A3 | |0 |0 |0 | |0
|0 |0 |
>
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~+
> |Length of Transfer |8 Bytes
|
>
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~+
> |Low Order Address | 000 |001 |010 |011 |100
|101 |110 |111 |
>
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~+
> |1st transfer | q |hb |hw |h3 |hd
|h5 |h6 |h7 |
> |Value driven on A3 | 0 |1 |1 |1 |1 |1
|1 |1 |
>
+------------------------------+---------+---------+---------+----------+---------+---------+----------+--------+
> |2nd transfer (if needed) | |l7 |l6 |l5 |ld
|l3 |lw |lb |
> |Value driven on A3 | |0 |0 |0 |0 |0
|0 |0 |
>
+---------------------------------------------------------------------------------------------------------------+
>
> Key:
>
> b = byte transfer w = 2-byte transfer 3 = 3-byte transfer d = 4-byte
transfer
> 5 = 5-byte transfer 6 = 6-byte transfer 7 = 7-byte transfer q = 8-byte
transfer
> h = high order ll = low order
>
> 8-byte operand:
>
+----------------------------------------------------------------------------------------+
> | high order byte | byte 7 | byte 6 | byte 5 | byte 4 | byte 3 | byte 2 | low order
byte |
>
+----------------------------------------------------------------------------------------+
OK, so... in this table you can see when the operand is a word it
requires a second transfer if the low order bits of the address are 3 or 7.
7 is understandable. after all, you're crossing a boundary, there. But,
3 is utterly baffling.
from this chart, when dealing with word-length operands I can surmise:
Address = # transfers for word
0x12345678 = 1 transfer
0x12345679 = 1 transfer
0x1234567A = 1 transfer
0x1234567B = 2 transfers
0x1234567C = 1 transfer
0x1234567D = 1 transfer
0x1234567E = 1 transfer
0x1234567F = 2 transfer
To me it makes no sense. xxxxB should be able to transfer in one go. Why
wouldn't it?
--
~Mike
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