So, I've been sort of reading this:

http://download.intel.com/design/intarch/manuals/27320401.pdf

I've had a pretty good idea of how the 8086 and 8088 deal with the 
system bus. But, I wanted to understand more about the later generation 
processors, so I started with the Pentium.

I'm on the section dealing with bus arbitration and cache coherency when 
there are 2 processors in the system. (This is the embedded version, I'm 
not sure if the full version is all that different)

It occurs to me that handling the cache when there are 2 parts vying for 
the same resource can get rather messy.

What I understand so far is: One process has the bus, and either reads 
or writes from/to the bus. The other processor watches the activity and, 
if it sees an address it has modified it tells the other processor, 
which passes bus control to the other, puts the data out on the bus, 
then returns control to the first processor.

Apparently, the bus can also be pipelined. I'm not exactly sure how this 
works, but the processors then have to agree on whether the operation 
actually can be put in a pipeline.

I can definitely see some potential for bottle-necks in a 
multi-processor system when dealing with the bus, since electrically, 
only one device can place data on the bus at one time. The nice thing 
is, in system design, you can design your bus the same for single or 
dual processors. Provided you've wired the proper signals together, and 
initialized the processors properly with software and certain pin 
levels, it's totally transparent to the rest of the system.

-- 
~Mike

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