clipka wrote:
> Someone with *any* idea what might go wrong here? (Even the weirdest ideas
> welcome, as they might happen to trigger some inspiration.)
> 

Maybe just a much better cache access and/or jump prediction as a result 
of using multiple cores? There are e.g. a few SSE2 instructions just to 
optimize the memory access.

Proper aligned memory on 16-byte boundaries as a side effect when using 
4 cores and misalignment when using just one?

Ok. Just wild thoughts, but speed optimization (or let's say the search 
for reasons that cause the lack of expected speed) for contemporary 
processors seems quite tricky.

-Ive

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