>> Actually, when I want to compile something, I usually just say "make 
>> foo". Otherwise GCC insists on naming it "a.out", which is very irritating.
> 
>   If you don't specify an executable name, how can gcc guess what is it
> that you want? Note that you can write something like:
> 
> g++ file1.cc file2.cc file3.cc

Now there's interesting. I didn't know you could actually compile 
multiple source files together; I was under the impression that in that 
case, you must manually invoke g++ several times, and then manually 
invoke ld to produce the final binary. (Or, more likely, write a 
makefile that does that.)

>   C++ inherits many things from C, good and bad.

Apparently so. ;-)

[I'm currently compiling a list...]

>> So there *is* a way to automate dependency analysis?
> 
>   The -MM option of gcc (which I use in that generic makefile I attached)
> auto-generates makefile dependencies for all the specified source
> files. Makefiles themselves (at least with gnu make) are so versatile
> that this can be used to completely automatize dependency building.

Well, that's a step up from manually writing a makefile, writing it 
wrong, and producing a binary that segfaults because it's built from 
incompatible object files...

>> This whole concept of having to manually write makefiles and manually 
>> write header files and so forth just seems tedious and error-prone.
> 
>   You don't need to manually write makefiles. Just use a generic one.

Has anybody come up with a tool for autogenerating header files yet?

(Presumably you'd need to edit such a file to remove references to 
things that aren't meant to be public, but at least the function names 
and signatures would match.)

-- 
http://blog.orphi.me.uk/
http://www.zazzle.com/MathematicalOrchid*

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