Warp wrote:

>   It becomes even more complicated when more than one processor (or core)
> needs to access the *same* RAM, which is the whole idea in SMP.

Oh yeah - that whole cache coherancy thing is a pretty big deal. (And 
one which the article goes into quite a bit of detail about later on.) 
Even more fun is trying to provide "atomic" access operations - which, 
as far as I can tell, absolutely *must* be done at the hardware level. 
There's just no way you could implement it in software.

>   You'll quickly see this requires quite a lot more than simple dumb
> passive electronic connections.

Bus arbitrartion, if nothing else...

>> And now they tell me that the latest designs use a serial link... this 
>> seems entirely counter-intuitive.
> 
>   It's a cost-effective necessity. The theoretical optimal situation
> would be if each core was directly connected to the memory controller
> with 64 (or 128 or whatever) wires. However, that would make the
> memory controller *very* complicated and *huge* (just imagine having,
> for example 8 cores, each connecting directly to the memory controller
> with 64 or 128 wires each), which translates to expensive and, in some
> cases, counter-productive.

I still kinda wish you could actually build a PC that had several GB of 
RAM running at the same speed as the CPU - but I'm guessing it might be, 
uh, slightly expensive?

[Presumably the only way it could be even remotely possible is if all 
the RAM was on the same die as the CPU. Damn, the die area would have to 
be *vast*! I hypothesize it would also eat electricity like candy, and 
perhaps get slightly warm too...]

-- 
http://blog.orphi.me.uk/
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