Invisible <voi### [at] devnull> wrote:
> I was aware that these days the RAM is about 20x slower than the CPU, 
> and that's why the CPU has to have a cache the size of a small planet to 
> achieve any performance whatsoever. But it's certainly news to me that 
> these days the communication involves a complex *protocol* instead of 
> just a direct passive electronic connection. Or that the refresh signal 
> has to come from outside the memory subsystem. Now I see why a "memory 
> controller" needs to exist.

  It becomes even more complicated when more than one processor (or core)
needs to access the *same* RAM, which is the whole idea in SMP. Nobody
gives it a second thought, but if you think about it, you'll quickly
notice that it's a very HARD problem. The problem is made extremely
harder because of the fact that all the processors/cores usually have
their own L1 cache, and this L1 cache must be in sync with the L1 cache
of all the other processors/cores if those have the same data.

  There's at least one opcode, more precisely cmpxchg, which Intel
guarantees to be atomic. That means that no two processors/cores will
compare&exchange the same memory location precisely at the same time.
Now, try to figure out *how* they do that, given that the memory location
being compared&exchanged may be in the processor's/core's local L1 cache.

  You'll quickly see this requires quite a lot more than simple dumb
passive electronic connections.

> And now they tell me that the latest designs use a serial link... this 
> seems entirely counter-intuitive.

  It's a cost-effective necessity. The theoretical optimal situation
would be if each core was directly connected to the memory controller
with 64 (or 128 or whatever) wires. However, that would make the
memory controller *very* complicated and *huge* (just imagine having,
for example 8 cores, each connecting directly to the memory controller
with 64 or 128 wires each), which translates to expensive and, in some
cases, counter-productive.

-- 
                                                          - Warp

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