Invisible <voi### [at] devnull> wrote:
> >> It puzzles me how this is possible.
> >>
> >> Sure, the Xeon probably has a much bigger cache and a slightly faster
> >> bus to the RAM chips. But is that *all* that makes it faster? Or is
> >> there more to it than that? I have no idea.
> >
> > The Pentium 4 line is notorious ineffecient in it's use of the clock
> > cycles, and each of it's generations just got worst of than the previous
> > one.

> Isn't this roughly the timeframe when AMD, Cyrix and half a dozen others 
> suddenly popped up with compatible chips running at the same clock speed 
> yet delivering massively increased performance, and Intel were all like 
> "oh crap!"?

  You are probably confusing it with the original Pentium. Cyrix and other
competitors were pretty much dead (or at least heavily struggling) by the
time of the P4. The only real competitor left was AMD.

-- 
                                                          - Warp

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>>> It puzzles me how this is possible.
>>>
>>> Sure, the Xeon probably has a much bigger cache and a slightly faster
>>> bus to the RAM chips. But is that *all* that makes it faster? Or is
>>> there more to it than that? I have no idea.
>>
>> The Pentium 4 line is notorious ineffecient in it's use of the clock
>> cycles, and each of it's generations just got worst of than the previous
>> one.
>
> Isn't this roughly the timeframe when AMD, Cyrix and half a dozen others
> suddenly popped up with compatible chips running at the same clock speed
> yet delivering massively increased performance, and Intel were all like
> "oh crap!"?
>
>> The problem was coined to an excessively long instruction pipe,
>> that got longer with each sub versions. It topped at over 200 steps...
>> It also greatly increased it's power requirments.
>>
>> With the new core2, they chopped that down around 30~40 steps with the
>> performance boost, and power consumption decrease, we can now experiment.
>
> Why would you build something that's vastly harder to design yet
> delivers awful performance? That doesn't make any sense. (I also don't
> see how it's *possible* to have a 200-step instruction pipeline, unless
> you were deliberately trying to be silly.)

Some high up conceptors and chief designers kept on increasing the pipe 
to get "beter prehemptive computation and branching choices 
optimisation". They saw improvements going from the pentium pro to the 
pentium II, and then from the pentium II to the pentium III using that 
strategy. They blinded themself to the fact that with the pentium III 
they had gotten slightly past the point of diminishing improvement to 
the point of NO improvement, and to the point of negative "improvement" 
with the pentium 4 family.
They where also blinded by a clock speed race that they started. The 
constant clock speed increace greatly contributed in hiding the decline 
in efficiency.

And, yes, the instruction pipe if the pentium 4's was sily, and kept on 
getting silyer over time. On the first P4, is was only about 120 
instructions long, on the last P4 generation, is was well over 200.

>
>> A Xeon system use a more advanced I/O architecture and beter memory
>> management. It's instruction pipe is relatively short. It probably have
>> beter cache management as well as larger cache, both L1 and L2. It's L1
>> cache is probably distinct to the L2 cache, while the pentiums L1 cache
>> address space was included in the L2 address space.
>
> Can we really attribute all the performance advantages of 10 years of
> R&D to a bigger cache and an on-board SDRAM controller?

Not ALL of it, but a good part of it.

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