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>> The 7400 is a quad 2-input NAND gate. In other words, it's a box with
>> four NAND gates in it.
>>
>> What's supposed to happen is that you connect pins 1 and 14 to a power
>> source, and the remaining pins are grouped into 3s. Each group is the
>> connections for a single NAND gate. When the inputs aren't connected,
>> the output pin is at logic high. When you connect both of the input pins
>> to the (+) rail, the output should go low.
>>
>> ...except this doesn't seem to happen. I swear to God I built circuits
>> like this when I was a kid, and it worked. But when I tried it as a
>> teenager, it wouldn't work for toffee. No idea why.
>
>
> Good grief Andrew, 7400s, did you rob a museum?
Maplin.
IIRC, they charge 21.22p per chip. (Presumably the 0.22p only makes a
difference if you buy hundreds of them...)
> Do you know the power consumption of TTL compared to CMOS?
TTL has the advantage that it doesn't break if you touch it. ;-)
> Besides pin 14 being Vcc and pin 7 ground.
OK. I was going from memory there.
> You cannot assume that inputs will
> float high you really should drive them high or low.
...?
--
http://blog.orphi.me.uk/
http://www.zazzle.com/MathematicalOrchid*
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On Sat, 15 Aug 2009 09:10:26 +0100, Orchid XP v8 <voi### [at] dev null> wrote:
>> Good grief Andrew, 7400s, did you rob a museum?
>
>Maplin.
>
When I worked for Motorola way back in the mid 70's. Maplin and RS were sold the
ICs that failed all the tests except the functional ones. So I would not trust
the quality very much.
>IIRC, they charge 21.22p per chip. (Presumably the 0.22p only makes a
>difference if you buy hundreds of them...)
>
I suppose I was spoilt as I always worked for a company that would let me have
them free. FWIW It was considered an educational thing to allow engineers some
time and materials for home jobs.
>> Do you know the power consumption of TTL compared to CMOS?
>
>TTL has the advantage that it doesn't break if you touch it. ;-)
>
Fair point although I never had much problem with ESD and CMOS as long as you
earth yourself.
>> Besides pin 14 being Vcc and pin 7 ground.
>
>OK. I was going from memory there.
>
I guessed as much.
>> You cannot assume that inputs will
>> float high you really should drive them high or low.
>
>...?
IIRC I think the specs said that TTL inputs would be at a logical 1 if there was
no connection. (Internal resistor to Vcc)
This was not the case with CMOS, so I was wrong saying that TTL had to be driven
either high or low. But it is good practice to drive your inputs in case there
are things in your physical circuit that might affect what you think will
happen. Such as dry joints, solder bridges, RF pickup etc.
--
Regards
Stephen
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>>> Good grief Andrew, 7400s, did you rob a museum?
>> Maplin.
>
> When I worked for Motorola way back in the mid 70's. Maplin and RS were sold the
> ICs that failed all the tests except the functional ones. So I would not trust
> the quality very much.
I'm told 10% resistors show a curios bimodel resistance distribution
too. ;-)
BTW... What tests are there *other* than functional ones?!
> FWIW It was considered an educational thing to allow engineers some
> time and materials for home jobs.
Indeed. I'm told Cadbury let their employees eat as much chocolate as
they want. Not so much for educational purposes, but because the amount
of chocolate that one employee can eat without being horrifyingly sick
is insignificant compared to the amount of chocolate they make per day...
>>> Do you know the power consumption of TTL compared to CMOS?
>> TTL has the advantage that it doesn't break if you touch it. ;-)
>
> Fair point although I never had much problem with ESD and CMOS as long as you
> earth yourself.
What voltage does CMOS use anyway? IIRC, TTL can be driven with a
triplet of 1.5 V batteries.
>> OK. I was going from memory there.
>
> I guessed as much.
It's been a while since I did all this.
> IIRC I think the specs said that TTL inputs would be at a logical 1 if there was
> no connection. (Internal resistor to Vcc)
Oh.
Well that would be a problem then. I was assuming it would be logic 0. o_O
> This was not the case with CMOS, so I was wrong saying that TTL had to be driven
> either high or low. But it is good practice to drive your inputs in case there
> are things in your physical circuit that might affect what you think will
> happen. Such as dry joints, solder bridges, RF pickup etc.
So connecting to the negative rail should give me 0, and connecting to
the positive rail should give 1?
--
http://blog.orphi.me.uk/
http://www.zazzle.com/MathematicalOrchid*
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On Sat, 15 Aug 2009 12:37:30 +0100, Orchid XP v8 <voi### [at] devnull> wrote:
>>>> Good grief Andrew, 7400s, did you rob a museum?
>>> Maplin.
>>
>> When I worked for Motorola way back in the mid 70's. Maplin and RS were sold the
>> ICs that failed all the tests except the functional ones. So I would not trust
>> the quality very much.
>
>I'm told 10% resistors show a curios bimodel resistance distribution
>too. ;-)
>
It would not surprise me but I could not say for sure,
>BTW... What tests are there *other* than functional ones?!
>
Well it was quite a while ago and I assume that they will have changed.
IIRC: Rise and fall times of the output, propagation delay of the gates, input
and output voltage range, operational temperature and humidly. There was a
centrifuge test up to 200 g for mil spec and a test where the ICs were dipped in
liquid helium and tested to see if there were any leaks on the encapsulation.
>> FWIW It was considered an educational thing to allow engineers some
>> time and materials for home jobs.
>
>Indeed. I'm told Cadbury let their employees eat as much chocolate as
>they want. Not so much for educational purposes, but because the amount
>of chocolate that one employee can eat without being horrifyingly sick
>is insignificant compared to the amount of chocolate they make per day...
>
I believe that too.
>>>> Do you know the power consumption of TTL compared to CMOS?
>>> TTL has the advantage that it doesn't break if you touch it. ;-)
>>
>> Fair point although I never had much problem with ESD and CMOS as long as you
>> earth yourself.
>
>What voltage does CMOS use anyway? IIRC, TTL can be driven with a
>triplet of 1.5 V batteries.
>
Why don't you look it up as I can't remember,
>>> OK. I was going from memory there.
>>
>> I guessed as much.
>
>It's been a while since I did all this.
>
>> IIRC I think the specs said that TTL inputs would be at a logical 1 if there was
>> no connection. (Internal resistor to Vcc)
>
>Oh.
>
>Well that would be a problem then. I was assuming it would be logic 0. o_O
>
:-)
>> This was not the case with CMOS, so I was wrong saying that TTL had to be driven
>> either high or low. But it is good practice to drive your inputs in case there
>> are things in your physical circuit that might affect what you think will
>> happen. Such as dry joints, solder bridges, RF pickup etc.
>
>So connecting to the negative rail should give me 0, and connecting to
>the positive rail should give 1?
Yes, by George you've got it!
:)
--
Regards
Stephen
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On 15-8-2009 13:37, Orchid XP v8 wrote:
>>>> Good grief Andrew, 7400s, did you rob a museum?
>
>> IIRC I think the specs said that TTL inputs would be at a logical 1 if
>> there was
>> no connection. (Internal resistor to Vcc)
>
> Oh.
>
> Well that would be a problem then. I was assuming it would be logic 0. o_O
Starting middle of September I'll be teaching digital technology in the
first year of the University of Applied Science in Amsterdam. If you
happen to be around, just drop in. I think I will do the 7400 in the
week of Sept 21. ;)
As others have said, the original TTL series by Texas Instruments acted
as if a one was present if left open. All other gates should do the same
because of backwards compatibility. That includes the CMOS pin
compatible replacements. I have actually seen rare default 0 gates but I
would consider those faulty.
When designing the rule is not to leave inputs open. Not even for gates
you don't use. One reason is that they could pick up interference which
could result in unpredictable behaviour. For CMOS gates it could also
result in useless power consumption. In any case the inputs are often
next to one another like in the 7400. It is just as easy to wire them
together (connecting them to ground (for NOR gates) or the positive rail
(for NAND gates) is often more complicated).
Oh, and if you want to build your own computer, I'd suggest using also
other components apart from the 7400.
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On Sat, 15 Aug 2009 22:08:45 +0200, andrel <a_l### [at] hotmailcom> wrote:
>Oh, and if you want to build your own computer, I'd suggest using also
>other components apart from the 7400.
Why? :P
Maybe some JK and D flip-flops
--
Regards
Stephen
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Orchid XP v8 schrieb:
>>> And then I got stumped by the fact that the gates don't appear to do
>>> what the diagrams suggest they should...
>>
>> In what way?
>
> The 7400 is a quad 2-input NAND gate. In other words, it's a box with
> four NAND gates in it.
>
> What's supposed to happen is that you connect pins 1 and 14 to a power
> source, and the remaining pins are grouped into 3s. Each group is the
> connections for a single NAND gate. When the inputs aren't connected,
> the output pin is at logic high. When you connect both of the input pins
> to the (+) rail, the output should go low.
>
> ...except this doesn't seem to happen. I swear to God I built circuits
> like this when I was a kid, and it worked. But when I tried it as a
> teenager, it wouldn't work for toffee. No idea why.
Maybe some other technology? While classic TTL gates (74xx) as well as
Low Power Schottky variants (74LSxx) would internally pull up
unconnected inputs, CMOS gates (74HCxx and 74HCTxx) would lack a pull-up
resistor, causing unconnedted inputs to float erratically.
To work properly, all input pins of a CMOS IC /must/ therefore be
actively pulled to either VCC or GND (a resistor is not required in that
case, as CMOS ICs draw virtually no current on static input pins, so you
can directly connect them to VCC or GND). It is even highly recommended
to even connect all input pins of unused gates in an IC package.
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Stephen schrieb:
>> What voltage does CMOS use anyway? IIRC, TTL can be driven with a
>> triplet of 1.5 V batteries.
>
> Why don't you look it up as I can't remember,
74HCxx: 2V to 6V (i.e. a doublet or triplet of 1.5 V batteries will do
fine, even when quite depleted already)
74HCTxx: 5V, +/- 0.5V (i.e. a triplet will probably do quite well if
still good)
Power consumption is virtually zero at low frequencies.
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>>> IIRC I think the specs said that TTL inputs would be at a logical 1
>>> if there was no connection. (Internal resistor to Vcc)
>>
>> Oh.
>>
>> Well that would be a problem then. I was assuming it would be logic 0.
>> o_O
>
> Starting middle of September I'll be teaching digital technology in the
> first year of the University of Applied Science in Amsterdam. If you
> happen to be around, just drop in. I think I will do the 7400 in the
> week of Sept 21. ;)
Heh. I doubt it - but nice idea. ;-)
> As others have said, the original TTL series by Texas Instruments acted
> as if a one was present if left open. All other gates should do the same
> because of backwards compatibility. That includes the CMOS pin
> compatible replacements. I have actually seen rare default 0 gates but I
> would consider those faulty.
>
> When designing the rule is not to leave inputs open. Not even for gates
> you don't use. One reason is that they could pick up interference which
> could result in unpredictable behaviour. For CMOS gates it could also
> result in useless power consumption. In any case the inputs are often
> next to one another like in the 7400. It is just as easy to wire them
> together (connecting them to ground (for NOR gates) or the positive rail
> (for NAND gates) is often more complicated).
Mmm. This I was not aware of...
> Oh, and if you want to build your own computer, I'd suggest using also
> other components apart from the 7400.
OOC, exactly how much space do you recon it would take to build 64KB out
of discrete NAND gates?
--
http://blog.orphi.me.uk/
http://www.zazzle.com/MathematicalOrchid*
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>> The 7400 is a quad 2-input NAND gate. In other words, it's a box with
>> four NAND gates in it.
>>
>> What's supposed to happen is that you connect pins 1 and 14 to a power
>> source, and the remaining pins are grouped into 3s. Each group is the
>> connections for a single NAND gate. When the inputs aren't connected,
>> the output pin is at logic high. When you connect both of the input pins
>> to the (+) rail, the output should go low.
>
> Good grief Andrew, 7400s, did you rob a museum? Do you know the power
> consumption of TTL compared to CMOS?
> Besides pin 14 being Vcc and pin 7 ground. You cannot assume that inputs will
> float high you really should drive them high or low.
I just looked up the wiring diagram.
It appears I had the right pins, they're just not numbered in the order
I was expecting.
--
http://blog.orphi.me.uk/
http://www.zazzle.com/MathematicalOrchid*
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