On 27/01/2011 03:26 PM, Warp wrote:
> Invisible<voi### [at] devnull>  wrote:
>> #2: You can compile a C++ program with
>
>>     g++ program.c++
>
>> However, for reasons beyond my comprehension, the result is always named
>> "a.out". You can tediously fix this using the -o option.
>
>    How else do you suggest the binary be named? "The same as the source
> file" is not a good answer because there may be (and often is) more than
> one source file. You can easily compile a multi-sourced program with
> "g++ *.cc". The -o parameter exists to tell the compiler the name of
> the binary.

I still don't see why it couldn't default to the name of the source file 
for the common case where only one is supplied, but anyway...

>    Anyways, if you find yourself compiling the same program again and again,
> that's exactly what makefiles are for, so you can simply write "make".

>    A makefile is, basically, what other SDKs call a "project" file. You can
> specify dependencies between files and rules on how to build files from
> other files (the idea, as with "project" files in other SDKs, is that files
> are built only if their source files change rather than every time).

Yes, I know what Make does and why that's useful. It's just that for 
what I'm trying to do, it's overkill. All I want to do is be able to 
quickly recompile a program each time I edit the source, without having 
to type in long complex commands.

>    Writing a makefile by hand can be somewhat tedious, but you only have
> to do it once.

...except that every time I add another program, I end up having to add 
another line to the Makefile to handle it.

I've got half a dozen trivial little C++ programs, and I want to be able 
to quickly recompile any of them. It's frustrating me that it's this 
difficult to do something so trivial.

The solution, as I just discovered, is to name the files *.cpp rather 
than *.c++; this apparently enables Make's implicit rules to fire. (I 
thought *.c++ was one of the "recognised" names, but apparently not...)

>    (This works because there is no file named 'all' in the current directory,
> so make will try to "build" it by running the command. Since the command
> doesn't create it, it will do so also the next time you run make, and so on.)

...or you could just mark "all" as a phony target. (Yes, I read that 
far. I've actually got a "clean" target in my Makefile, for example...)

>    A full-fledged makefile would build object files from each single source
> file, and then link those object files into the final binary. This allows
> compiling only those object files that really need it, so if there are
> many source files, it will speed up compilation.
>
>    Of course the rules for this to work become very complicated, and nobody
> in their right minds would write them by hand. There exist tools to
> automatically create a makefile from a bunch of source files

...which is all very interesting, but overkill for what I'm trying to do.

I've played with things like the Makefile for GHC, which supports 
compiling the compiler, compiling the compiler with the compiler you 
just compiled, running the test suite, building the user manual, 
building the library documents, running the standard benchmark set, and 
polishing your shoes for you. It's neat that you can do all that, but 
it's far beyond my simple needs.

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