Am 14.06.2010 18:58, schrieb Darren New:
> clipka wrote:
>> I don't think so. Essentially, all you need to decode an address is a
>> huge AND gate with some inputs inverted
>
> In theory true. In practice, there's a certain amount of fan-in you can
> handle in any one gate. The limit is about 8 inputs, afaik. My knowledge
> on this particular bit is probably several fab generations out of date.

Even then, you'd have some log8(N) dependency of gate levels needed, 
where N isn't even the amount of memory, but the number of address lines.

1 level:   8 address lines - up to 256 words (*)
2 levels: 64 address lines - up to 16 Exawords

(* where the word size solely depends on your data bus width)

If main memory sizes should increase with the same speed as today, that 
should give us another 20 to 30 years until a computer for private or 
office use will need 3 levels of address decoding gates in its RAM modules.

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