Am 14.06.2010 17:12, schrieb Invisible:
> clipka wrote:
>
>> (1) Home computers were toys.
>
> I saw at least one employee using a company-purchased C64 to run
> accounting software to do actual, productive work.
>
> They might be considered toys *now*...
>
>> (2) Capacity of memory basically has nothing to do with access speed.
>
> Really? So having more bits to decode requiring more address decode
> logic doesn't affect speed in any way?

I don't think so. Essentially, all you need to decode an address is a 
huge AND gate with some inputs inverted (and no, multi-input gates are 
/not/ normally designed as a tree of 2-input gates - they're simply 
extend on the 2-input gate design by adding just a few inputs and 
transistors more). Of course you need more of those gates, and therefore 
stronger drivers for the address lines to deal with the parasitic 
capacitance of the gates' inputs.

 > And neither does a larger die
> area necessasitating longer traces?

That, yes. But that's negligible compared with the distance between CPU 
and memory slot.

AFAIK, the most time-consuming thing about DRAM is the time it takes to 
charge, discharge or read out the capacitors comprising the memory cells.

> I gather that part of the problem is that having traces on the
> motherboard operating into the GHz frequency range isn't very feasible.
> (For reasons such as trace length and electronic interference.) But that
> would still mean that theoretically you could make a single chip that
> contains a couple of CPU cores plus (say) 2GB of RAM. The fact that
> nobody has ever done this indicates that it isn't possible for whatever
> reason.

I guess it's impractical, because...

(1) RAM requirements are pretty different, so you'd need a lot more CPU 
models (which would skyrocket the development, maintenance and 
production set-up costs per CPU) - and you couldn't just buy a few extra GB.

(2) You wouldn't win much speed because DRAM technology is inherently 
slow, and SRAM technology (as used in caches) is prohibitively large

(3) I might be wrong, but I guess producing DRAM memory in a 40nm 
process would be ineffective: You do want certain minimum dimensions for 
the capacitors and insulation anyway, in order to reduce self-discharge 
effects.

(4) Integrating 2GB into the CPU would require a lot of additional die 
space even with DRAM, increasing the per-die production cost - not only 
because you get less CPUs out of a wafer, but also because increasing 
the die space gives you an increased per-die probability of a failure, 
reducing production yield.

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