Invisible wrote:

> http://www.play-hookey.com/digital/jk_nand_flip-flop.html
> 
> This is significantly simpler than I had imagined! ;-)

An RS flip-flop is not difficult to construct. I quickly discovered that 
if you connect to gated RS latches together, and connect both gate pins 
to the flip-flop's clock pin, but with one signal inverted, you get a 
clocked flip-flop. (Gratifyingly, I discovered the website above and 
found the exact same circuit design. So apparently I was right!)

Converting a gated latch or a clocked flip-flop from RS-type to D-type 
is a trivial matter of adding an inverter. Making a toggle flip-flop 
just requires you to take a clocked D flip-flop and connect the inverted 
output back to the data input. The clock pin then becomes the toggle. So 
far so good.

Now... how in the name of goodness do you add UNclocked set and reset 
pins?? o_O

It's easy to make a T flip-flop, but maddeningly complicated to add 
unclocked set/reset pins. I end up adding dozens and dozens and dozens 
of extra gates, and the implementation is *still* as buggy as hell!

Obviously, there has to be an easier way. So I looked up the circuit 
diagram for the 7474, and... oh.

I've built it in a simulator, and I can confirm that it works, but I 
have utterly no clue as to *why* it works!

It's basically three RS latches, but trying to follow all the signal 
paths is quite challenging. Next, they used NAND latches rather than NOR 
latches. That means that the control inputs are inverted. >_< On top of 
that, they used a small trick: 3-input gates. That means that each pair 
of NANDs is simultaneously an RS latch *and* it performs an operation to 
combine 4 inputs into two inputs (set/reset).

After expending significant time and energy confusing myself with logic 
tables, I eventually figure out what, in effect, you've got a normal 
(low-triggered) RS latch with a 2-input NAND gate setting on each input. 
So I figured up an equivilent circuit and tried it out.

It doesn't work. It doesn't even partially work.

After about, oh, an hour maybe, I discovered the reason why: You know 
how having both set and reset lines active simultaneously is an unstable 
configuration for an RS latch? Well it turns out that a NAND latch with 
inverted inputs is _not_ equivilent to a NOR latch; there is a single 
difference between them. In the unstable configuration, a NOR latch sets 
both Q and /Q to 0, while a NAND latch sets them both to 1. >_<

Not only that, but this strange flip-flop circuit seems to *depend on* 
this specific behaviour. Like, one of the latches is permanently driven 
in this configuration, except when certain lines are activated! Damnit!

Well anyway, I modified my circuit, and it *finally* it works correctly. 
But I still don't have a clue why... Time for further study. :-/

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