Warp wrote:

> Stefan Viljoen <pov### [at] polardcom> wrote:
>> From http://www.worldofspectrum.org/faq/reference/sereference.htm:
> 
>> ---
>> Memory is paged in 8K banks from either the DOCK or the EX bank
> 
>   This talks about the RAM, not the reason why the pixels are arranged as
> they are.

Hmm. Wouldn't it make sense? The video display is just visible RAM by 
definition... isn't it? Or am I mistaken?

I. e. if you can only address an 8K page at a time, and access to memory is 
limited by the last-triggered interrupt, and the limitations / maximum word 
size of your architecture.

I. e. on one tick you can address even lines.

On the other you can address odd lines.

Given that 8K paging is your "chunk limit", wouldn't that explain why the 
video pixels are arranged in such a way as you describe? 

Everything fits if you assume you can only address 8192 bytes at a time 
during any given interrupt - you CANNOT address the whole screen, because 
your word size is too small.

Contrast with an IBM PC with a VGA card. You can comfortably get a linear 
address into the entire 320x200 screen (64000 bytes) with any of the CPU's 
16 bit address registers. With an 8 bit address register you can't? 

So you arrange your video RAM (which you can't all address at once with an 8 
bit address register) to "give" you alternating blocks on an interrupt which 
is acted upon by your memory controller, effective switching contexts with 
each tick?
-- 
Stefan Viljoen

Post a reply to this message