Stefan Viljoen wrote:

> Warp wrote:
> 
>> Stefan Viljoen <pov### [at] polardcom> wrote:
>>> Warp wrote:
>> 
>>> >   The first 32 bytes in the screen memory represented the first line
>>> >   of
>>> > pixels (256 of them). The next 32 bytes represented the *eigth* line
>>> > of pixels. The next 32 bytes represented the *sixteenth* line of
>>> > pixels, and so on, until you get to one third of the screen, ie. 8
>>> > such groups of 32 bytes, after which the next 32 bytes represented the
>>> > second line
> 
> Which ZX Spectrum video mode was this?
> 
> 'pedia says there are / were lots and lots of them - what mode does this
> arrangement refer to? The lowest res one?
> 
> Or were all the modes arranged similarly to this way, only with longer
> lines and "quicker" jumps?

From http://www.worldofspectrum.org/faq/reference/sereference.htm:

---
Memory is paged in 8K banks from either the DOCK or the EX bank, but these 
banks are mutually exclusive - you cannot page in a bank from both 
simultaneously. Bit 7 of port 0xff determines which bank to use (0=DOCK, 
1=EX-ROM). Port 0xf4 determines which banks are to be paged in with each bit 
referring to the relevant bank (0-7 or 0'-7'). When memory is being paged, 
interrupts should be disabled and the stack should be in an area which is 
not going to change.

On a TC2048, BASIC is contained in the 16K ROM area and banks 0-7 and 0'-7' 
are not normally available, while on a TS2068 part of the BASIC is stored in 
an 8K ROM in bank 0' and cartridges plugged into the dock use banks 0-7. On 
the SE each of these banks is connected to 64K of RAM, providing an 
additional 128K in addition to the base RAM.

The contended memory timings for the SE are unknown but should be similar to 
that for the 48K machine, except that the pattern starts at a different 
number of T-states after the interrupt, than the usual 14335. Odd banks in 
the 128 scheme are contended.
---

"Memory is paged in 8K banks from either the DOCK or the EX bank, but these 
banks are mutually exclusive - you cannot page in a bank from both 
simultaneously."

and

"The contended memory timings for the SE are unknown but should be similar 
to that for the 48K machine, except that the pattern starts at a different 
number of T-states after the interrupt, than the usual 14335. Odd banks in 
the 128 scheme are contended."

What does that imply? It seems as if the reason for the knit-one-slip-one 
video RAM approach was the way the Speccy handled interrupts, and / or the 
hardware being incapable of paging more than 8K at a time? (8192 bytes / 256 
bytes per line = 32 ?)

I. e. on one interrupt tick you can get the first 32 columns of line one, on 
the next tick the first 32 columns of line sixteen, etch. - due to the 
limitations of the architecture's memory handling paradigm of "max 8k 
blocks" only?
-- 
Stefan Viljoen

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