Orchid XP v8 wrote:
> Right. So just to make sure I understand this... you're saying the cache 
> is managed in chunks of 32 bytes at a time? Like, if you fetch 1 byte of 
> data from memory, 32 bytes will be loaded into the least recently used 
> cache line? (Or whatever the cache policy is.)

That's how I understand it. I believe it's more accurate to say that the 
bus between the memory and the registers is actually 32-bytes wide. I 
may be mistaken in that, tho.

> Are the cache lines aligned in any sort of way? (I'm wondering if it 
> grabs 32 bytes at the nearest 32-byte boundary or not.)

I'm also pretty certain it is on 32-byte boundaries. Otherwise, the 
addressing logic winds up being slower than the time you save caching stuff.

-- 
Darren New / San Diego, CA, USA (PST)

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