Warp wrote:
>   Intel processors have reordered instructions automatically since the
> Pentium Pro (AFAIR).

I think getting the compiler to do this was one of the basic ideas 
behind RISC, until they figured out that it meant you had to recompile 
your source code for every minor rev of your CPU. :-) I even remember 
that the compiler was supposed to know how long instructions took, so 
you didn't have any hardware to wait for an instruction to complete 
before you started using its results.

A lot of the RISC stuff that sounded real cool actually turned out to be 
a bad idea if you wanted to run the same code on multiple compatible CPUs.

 >   If the GC'd language doesn't reorder elements in memory to be more
 > cache-friendly, that can have a rather large penalty in speed.

Hmmmm... I've never heard of that. I wonder how easy it is to figure out 
how to arrange things (based on compile-time or run-time information 
rather than intuitive understanding of the algorithm) to make cache 
misses mless common.

-- 
Darren New / San Diego, CA, USA (PST)

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