Darren New <dne### [at] sanrrcom> wrote:
> I don't think that's sufficient to make it a RISC processor. That would 
> mean both the PDP-11 and the X-560 were RISC processors.

  Who says they weren't?

> The X-560 had 
> built-in instructions for COBOL data types, string manipulation (aka 
> block moves/compares/character set and case conversions/etc), 
> instructions that would do things like push a word on a stack whose 
> pointer was in a particular register and set the condition bits to stack 
> full/empty/almost full/almost empty, etc. Yet it had 7 bits of opcode, 
> one "indirect" bit, four bits of register ID, then either three bits of 
> index register and 17 bits of address, or 20 bits of absolute 
> (immediate) data. Very straightforward enough that I can still remember 
> how the opcodes were laid out after 20 years not using it. Pretty much 
> all the microcoded CISC machines were like that, especially those 
> expected to be programmed in assembler.

  I don't think RISC has been ever defined to mean "you can only perform
very simple operations with a single opcode". RISC stands for *reduced*
instruction set computer, not *simplified* instruction set computer.
Just because the total amount of different instructions may be small
(eg. because only 7 bits of the opcode have been reserved for the
instruction, and thus the number of different instructions is limited
to 128), that doesn't mean that an instruction couldn't perform very
complicated things.

  I don't really understand where the concept of a RISC opcode being
*simple* has come from.

  What makes RISC processors simpler is that their fetching and decoding
steps, pipelines and code caches are simpler because all the opcodes have
exactly the same size and the meaning of the bits in each opcode has
been fixed. CISC processors are more complicated because of variable-sized
opcodes which can contain almost anything.

> You'd have to talk about addressing modes, pipelines, generalness of 
> registers, etc.  Sure, the original RISC processors had a very simple 
> model so they could fit more registers, but I think we've gone past that 
> now. What you describe might be true of *typical* RISC processors and 
> untrue of *typical* CISC processors, but I think everything's complex 
> enough now that you need to measure things on multiple dimensions in 
> order for it to make any sense.

  It's not a question of simple or complicated.

-- 
                                                          - Warp

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