> I got the patch from http://www.swallowtail.org/naughty-intel.html

	Ok, same here.

> My Athlon64 is a Venice core, which does include sse3
> support.

	Ah, right.  So the small slowdown you see from -xW to -xP should be
due to the use of SSE3 indeed.  I suppose it's because of microarchitecture
differences between Intel's and AMD's implementations of SSE3 that makes
icc produce slower code here.
	In any case you'd better stick with gcc on the k8  :-)

	- NC

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