In article <3d5825ba@news.povray.org> , "Francois Piednoel" 
<fra### [at] intelcom> wrote:

> On the other side, we saw a lot of funky thinks when you have multithreaded
> applications, like video decoding, or 3D pipelines using multiple threads,
> because some time, the CPU2 ask a write combine from the CPU1 and that is
> colliding with the regular memory traffic.

A bit off-topic:  Recently someone suggested to me that something like this
would be efficient* on x86 processors in a multiprocessor environment. This
is assuming two (or more threads) access the same data structure and one
thread is writing to it:

volatile int flag;        // toggle between matrix 1 and 2 to
struct {                  // allow one thread to modify matrix1
    double matrix1[4][4]; // and one or more others to read
    double matrix2[4][4]; // the other matrix2 or vice versa
}

Is there any information for programmers by Intel available (to the public)
regarding code like the above compared to more abstract ways of doing
parallel access?  Or, more general about parallel read/write access pitfalls
and performance suggestions on x86 systems?

    Thorsten

* At least more efficient than a simple lock and using a single data
structure assuming there are many (at least tens of thousands or more per
second) locks/unlocks.

____________________________________________________
Thorsten Froehlich
e-mail: mac### [at] povrayorg

I am a member of the POV-Ray Team.
Visit POV-Ray on the web: http://mac.povray.org

Post a reply to this message